For submission procedures and special announcements, please check the individual workshop webpages for specific information.
For general questions about workshops at PACT or to propose an additional workshop, please contact the workshop chair Martin Schulz.
Organizers:
Wilson Rivera and Jaime Seguel, University of Puerto Rico Mayaguez, USA
The purpose of this workshop is to provide an open forum for researchers from
hardware and software areas to present, discuss, and exchange research-related
ideas, results, and experiences in the area of adaptive middleware for
computational Grids.
Organizers:
Diana Marculescu, Carnegie Mellon University,
and J. Ramanujam, Louisiana State University, USA
Organizers:
Sandro Bartolini, University of Siena, and
Pierfrancesco Foglia and Cosimo Antonio Prete, University of Pisa, Italy
Due to the ever-increasing gap between CPU and memory speed, there is a great
interest in evaluating and proposing processor, multiprocessor and system
architectures dealing with the "memory wall" problem. In this scenario, memory
performance issues can be better addressed when considering system architecture
and application domain in a joint manner. In fact, it is the combined effect of
the applications and the system on which they are executing that stresses the
memory subsystem and pushes towards specific solutions. Typical architectural
choices include single processor vs. multiprocessor solutions, single chip vs.
COTS design, superscalar, multithreaded or VLIW architectures. Application
domains encompass commercial (Web, DB, e-business, and multimedia), embedded
(personal, mobile, automotive, automation and medical), networking applications,
etc.
The MEDEA-2003 Workshop wants to be a forum for academic and industrial
people to meet, discuss and exchange their ideas and experience on the design
and evaluation of architectures for embedded, commercial and general purpose
systems. Main topics are memory performance issues and solutions in the various
application domains.
The purpose of this workshop is to provide an open forum for computer
scientists, computational scientists and engineers, applied mathematicians, and
researchers to present, discuss, and exchange research-related ideas, results,
works-in-progress, and experiences in the areas of architectural, compilation,
and language support for problems in science and engineering applications.
Sunday, September 28th (all day)
AGridM 2003: Workshop on Adaptive
Grid Middleware
Scope:
Grid computing research focuses on building a large-scale
computing infrastructure by linking computing facilities at many distributed
locations. By analogy with the electric power Grids, such systems are known as
computational Grids. Significant effort has been spent in the design and
implementation of middleware software for enabling computational Grids. These
software packages have been successfully deployed and it is now possible to
build clusters beyond the boundaries of a single local area network. However,
the challenging problem of dynamically allocating resources in response to
application requests for computational services remains unsolved. Adaptive
middleware is software that resides between the application and the computer
operating system and enables an application to adapt to changing availability of
computing and networking resources.
Workshop webpage:
http://ece.uprm.edu/agridm2003
Saturday, September 27th (all day)
COLP 2003:
Workshop on Compilers and Operating Systems for Low Power
Scope:
Power consumption has increasingly become important in computer
systems. Current designs of processor cores are predicting power
figures above 100 Watts. The management of power consumption while
simultaneously delivering acceptable levels of performance is
becoming a critical task with the proliferation of application
domains such as wireless communication and embedded signal
processing. In addition, it has become increasingly important to
manage power consumption in high-performance, general purpose
microarchitectures. It has been forecast that, without significant
advances in design for low power, processors of the future will
consume hundreds of watts of power. We believe that a synergistic
hardware-software approach is required. A lot of attention has been
paid to optimizing power at the circuit and gate levels. Recently,
power optimizations at the architecture and software (i.e., compiler,
operating system, and application) level have begun to receive
increasing attention. The purpose of this workshop is to draw
together researchers and practitioners concerned with compiler and
operating system support for low power for a stimulating exchange
of views. Presentations from invited speakers from both the industry
and academia will provide insights into emerging issues related to
this area of research.
Workshop webpage:
http://www.ece.lsu.edu/jxr/colp03.html
Saturday, September 27th (afternoon)
MEDEA 2003: MEmory performance:
DEaling with Applications, systems and architectures
Scope:
MEDEA-2003 aims to continue the high level of interest in the
first three MEDEA Workshops held with PACT'00, PACT'01 and PACT'02.
Workshop webpage: http://garga.iet.unipi.it/medea03/
Sunday, September 28th (all day)
SNAPI 2003: Workshop on
Storage Network Architecture and Parallel I/Os
Organizer:
Qing (Ken) Yang, University of Rhode Island, USA
Scope:
Data are the "life-blood" of computing and the main asset of any
organization. Therefore, disk I/O and data storage on which data reside are
becoming "first class citizens" in today's information world. This workshop
intends to bring together researchers and practitioners from academia and
industry to discuss cutting edge research on parallel and distributed data
storage technologies. By discussing ongoing research, the workshop will expose
participants to the most recent developments in storage network architectures
and parallel I/O.
Workshop webpage:
http://www.ele.uri.edu/tcca/SNAPI_CFP.html
Saturday, September 27th (all day) and Sunday, September 28th (morning)
SHPSEC 2003:
Workshop on Hardware/Software Support for Parallel and Distributed Scientific
and Engineering Computing
Organizers:
Minyi Guo, University of Aizu, Japan, and
Laurence Tianruo Yang, Francis Xavier University,
Canada
Scope:
The field of parallel and distributed processing has obtained
prominence through advances in electronic and integrated technologies beginning
in the 1940s. Current times are very exciting and the years to come will witness
a proliferation in the use of parallel and distributed systems, or
supercomputers. The scientific and engineering application domains have a key
role in shaping future research and development activities in academia and
industry.
Workshop webpage:
http://juliet.stfx.ca/people/fac/lyang/pact03-spdsec/