As hinted at by the name, each CISC instruction given to the computer did quit a bit. With lack of memory in computers at the time, this worked well: less time worrying about little things saved in memory.
As computers increased speed in 1980's, people failed to realize that CISC computers were holding speeds down. After all, CISC had always been used, and computers were getting faster.
Yet, as RISC computers, which did less with each instruction, began to come out of the closet, it was realized that CISC had many liabilities. Specialized, complex instructions allowed less freedom in programming and memory allocation.
Caches decreased the time it took to get to memory. Thus the program length increase that results from the use of RISC, with all its simpler instructions, was now acceptable.
Another problem that became evident for CISC was its difficulty to keep up with improvements in pipelining. As myriad pipelines were used in parallel, instructions were passed more quickly, CISC instructions made it difficult to use pipelines because of differing lengths of instructions. For example, when instructions are being shuffled between several pipelines, if each varies in length, then instructions will soon come out of order, the next necessary in instruction stuck in a pipeline behind a very long instruction. RISC avoided this problem by keeping every instruction at the same length, making it easier for instructions to be pipelined in parallel.
Because of these factors, it became evident that RISC was the way to go. While CISC still exists, it looks more and more like RISC
As mentioned, instructions are of a uniform length.
Instruction sets were also streamlined to contain important and efficient instructions, refraining from instructions that copied higher level languages or were simply interesting.
The method by which memory was addressed was simplified. Any complex references were split up into several instructions.
The number of registers was increased and used to hold frequently-used variables. Thus RISC processors have at least 16 and as many as 64 registers.
Finally, delayed branches were created. In other words, when a branch in the code the computer was processing occurred (that is, there is an unanticipated call to another section of the program that necessitates another call to memory), instead of stalling the pipeline to retrieve the instructions that were branched to, the computer added a delaying instruction behind the branch that either did something useful while the other instructions were called, or at worst did nothing at all.
Of course, there is much more to HPC than RISC.
List of computer changes taken from Dowd